1. Field of the Invention
The present invention relates to a package structure, in particular, to a stacked type semiconductor device package structure.
2. Description of Related Art
In today's information society, users all seek electronic products with high speed, high quality and multiple functions. In terms of the product exterior appearance, electronic product designs reveal a trend of light weight, thinness and compactness. Therefore, various semiconductor device package techniques such as stacked-type stacked type semiconductor device package technique are proposed.
In the stacked-type semiconductor device package technique, several semiconductor devices are perpendicularly stacked together to form a package structure so that the package density is improved and the dimension of the package is decreased. Furthermore, by using three-dimensional stacking method to decrease the path length of the signal transmission between the semiconductor devices, rate of the signal transmission is improved and the semiconductor devices with different functions can be combined in the same package.
A conventional stacked-type semiconductor device package technique stacks chips on a wafer carrier having through silicon vias (TSV) to perform a wafer level package, and cutting off the wafer carrier with a molding compound thereon to form plural individual package units. Each of the individual package units may be connected to an external circuit board through solder balls formed on the bottom surface of the wafer.
However, the conventional stacked-type semiconductor device package technique first forms the solder balls on the bottom surface of the wafer, and then directly disposes the wafer carrier with the solder balls on the carrier and embeds the solder balls into an adhesive layer on the carrier. And, after the steps of a wafer level package is completed and the wafer carrier and the carrier are separated, the solder balls on the bottom surface of the wafer carrier are exposed. Therefore, when a solder ball having a larger size is formed on the bottom surface of the wafer carrier, it is difficult to firmly bond the solder ball in large size to the adhesive layer on the carrier, and thus the reliability of the package process is inferior.